1. Field of the Invention
The present invention relates generally to a static random access memory(SRAM)system, and more particularly to a static random access memory system with a compensating-circuit.
2. Description of the Prior Art
As semiconductor devices, such as the Metal-Oxide-Semiconductor device, become highly integrated the area occupied by the device shrinks, as well as the design rule. With advances in the semiconductor technology, the dimensions of the integrated circuit (IC) devices have shrunk to the deep sub-micron range. When the semiconductor device continuously shrinks in the deep sub-micron region, some problems described below are incurred due to the scaling down process. To meet customer demand for small size and low power products, manufacturers are producing newer integrated circuits (ICs) that operate with lower supply voltages and that include smaller internal sub-circuits. Many ICs, such as memory circuits or other circuits such as microprocessors that include onboard memory, include one or more SRAM cells for data storage. SRAMs cells are popular because they operate at a higher speed than dynamic random-access-memory (DRAM) cells, and as long as they are powered, they can store data indefinitely, unlike DRAM cells, which must be periodically refreshed.
Static random access memory (SRAM) cells typically provide memory storage for bits that can be rapidly read from and written to. Conventional structure of Static random access memory (SRAM) cell is a six-transistors SRAM cell, which means six transistors are used to form a SRAM cell. In general, advantages of six-transistors SRAM cell at least include high speed and possibility of low supply voltage. By unfortunately, one unavoidable disadvantage is that area of six-transistor SRAM cell is large, and the disadvantage is more serious and it is desired to overcome the disadvantage by either improving structure of six-transistors SRAM cell or providing a new SRAM cell. Therefore, four-transistors SRAM is present to replace the conventional six-transistors SRAM cell. Clearly, owing to number of used transistor is decreased, occupied area of four-transistors SRAM cell is less than six-transistors SRAM cell. Thus, four-transistors SRAM cell is more suitable for ICs whenever sizes of ICs are reduced, even four-transistors also meets some disadvantages such as higher off-state leakage current of PMOS. More introduction of four-transistors SRAM cell can be acquired by referring to IEEE IEDM 98-643 to IEDM 98-646, U.S. Pat. No. 5,943,269, U.S. Pat. No. 6,091,628, U.S. Pat. No. 6,044,011, U.S. Pat. No. 6,011,726, U.S. Pat. No. 5,751,044.
In a typical SRAM cell having six field effect transistors (FET transistors), there are a first inverter formed by two of the FET transistors and a second inverter formed by other two of the FET transistors between power and ground terminals. The first and second inverters are cross-coupled such that at a first storage node, the output of the second inverter is tied to the input of the first inverter, and at a second storage node, the output of the first inverter is tied to the input of the second inverter. The first and second cross-coupled inverters form latched wherein one of the storage nodes is pulled low and the other storage node is pulled high. The other two of the six transistors are pass FET transistors controlled by a wordline signal on a wordline conductor. One of the pass transistors is coupled between a bitline and the first storage node. The other pass transistor is coupled between a bitline# and the second storage node. With the pass transistors off, the first and second storage nodes are insulated from the bitline and bitline#, although there may be some leakage.
In a reading procedure, data and data# signals are precharged high on the bitline and bitline#, respectively. When the wordline is asserted, one of the storage nodes is low and the other is high. The low storage node begins to pull either the data or data# signal low depending on the state of the memory cell. A sense amplifier senses a difference between the data and data# signals and accelerates the fall of whichever of the data or data# signals corresponds to the low storage node until the storage node is low. The high storage node remains high and the sense amplifier may pin the storage node high through the data or data# signal (depending on the state of the memory cell). Accordingly, the reading procedure causes the storage nodes to remain at the same logic states after the wordline signal is de-asserted. The sense amplifier provides a signal indicative of the state.
In a writing procedure, circuitry in a sense amplifier causes one of the data or data# signals to be high and the other to be low in response to whether a high or low value has been written into a write buffer. When the wordline signal is asserted, if the current state of the first and second storage nodes is the same as that of the data and data# signals, the first and second storage nodes remains the same. If the current state of the first and second storage nodes is different than that of the data and data# signals, one of the storage nodes is pulled down while the other storage node is pulled up. When the states of the first and second storage nodes in the latch formed of the two cross-coupled inverters changes, the latch is said to flip states. Unlike dynamic random access memory (DRAM) cells, SRAM cells are not required to be refreshed to maintain their state. Rather, as long as the power is supplied to the power terminal and absent leakage, the voltage states of the first and second storage nodes are stable in the latch of the cross-coupled inverters.
As CMOS process technology progresses, the increasing leakage current is becoming critical and acts as a noise source for sense amplifier of memory. In the conventional SRAM, the increased bitline leakage current will induce read/write incorrect operation. The conventional SRAM leakage problem is shown below FIG. 1, memory system 100 includes a column 120 with a plurality of memory cells 110, wherein the column 120 is formed by a plurality of memory cells 110 coupled with a first bitline 130A and a second bitline 130B; a Bitline conditioning circuit 140 is coupled with the first bitline 130A and the second bitline 130B to precharge the first bitline 130A and the second, bitline 130B, individually; each memory cell 110 is coupled with a wordline 150 and each wordline 150 is also coupled with the first bitline 130A and the second bitline 130B, individually. As shown in FIG. 1, it schematically illustrates a first state V1 and a second state V2 of each memory cell 110 in the column 120.
First of all, the Bitline conditioning circuit 140 performs a pre-charge operation to make the first state V1 becomes one (V1=1) and the second state V2 becomes zero(V2=0)of every memory cell 110, that is, the first state is higher than the second state of every memory cell 110. If the first wordline 150A is selected to perform a read/write procedure and other wordlines 150 are not selected, the first wordline 150A will be ON to make the first state V1 become zero (V1=0) and the second state V2 become one (V2=1) in the first memory cell 110A, but the first state V1 becomes one (V1=1) and the second state V2 becomes zero (V2=0) in other memory cells 110, that is, in which for the first memory cell 110A, the first state V1 is lower and the second state V2 is higher, but for other memory cells 110, the first state V1 is higher and the second state V2 is lower. It will result in leakage with respect to the second bitline 130B and the second state V2 of all memory cells 110 will tend to balance. If amount of the memory cells 110 in the column 120 is larger more and more, the second state V2 of the first memory cell 110A will be becoming lower due to the leakage issue, and further, the leakage of the second bitline 130B on the first memory cell 110A is increased as time. When a normal access (read/write) operation happens, the second state V2 of the first memory cell 110A will be becoming “0” from “1” due to the leakage issue, and hence, that will be erroneous judgement to form “error”.
To keep leakage low, the threshold voltages have to be kept relatively high in the conventional SRAM process, and the threshold voltages of transistors of the memory cells may be higher than for transistors of other portions of the integrated circuits containing the memory cells. However, keeping the threshold voltage high also decreases the switching speed and effects cache performance thereof. For forming the SRAM process, this method that utilizes adjusting the threshold voltage in the SRAM process is difficult to be performed, and it also increases the process costs. In accordance with the above description, a new and improved method and the structure thereof for preventing the leakage in SRAM is therefore necessary in the deep sub-micron technology of semiconductors, so as to raise the performance of SRAM.